Method and means for protecting an ac electric system from short circuits by a distance relay having quadrilateral characteristics



Oct. 28. 1969 SHIRO SUZUKI r 3,475,655

TRIC SYSTEM FROM ELAY HAVING QUADRILATERAL CHARACTERISTICS METHOD AND MEANS FOR PROTECTING AN AC'ELEC SHORT CIRCUITS BY A DISTANCE R 2 Sheets-Sheet 1 Filed April 11, 1967 NNH s: Q a; E: E 3: Z VNH 2 E w: m E 3 nu SUE- a w 1 3 2 SE M Q: N 7 .N E t E: NN N: w W E n z 3,475,655 SYSTEM FROM AVING Oct. 28, 1969 sumo SUZUKI 2 Sheets-Sheet 2 Filed April 11; 1967' FIG? FIGS

COMMON FIGS United States Patent 3,475,655 METHOD AND MEANS FOR PROTECTING AN AC ELECTRIC SYSTEM FROM SHORT CIRCUITS BY A DISTANCE RELAY HAVING QUADRILAT- ERAL CHARACTERISTICS Shiro Suzuki, Tokyo, Japan, assignor to Meidensha Electric Mfg. Co. Ltd., Tokyo, Japan Filed Apr. 11, 1967, Ser. No. 629,964 Claims priority, application Japan, Apr. '11, 1966, 41/22,784 Int. Cl. H0211 7/26 U.S. Cl. 317-27 4 Claims ABSTRACT OF THE DISCLOSURE A quadrilateral distance relay having six simulated impedance elements for generating out of phase voltages and means for comparing the relative phases of the voltages to detect fault condition in a transmission line.

This invention relates to a distance relay having quadrilateral characteristics. A so-called phase comparison, static type distance relay has the advantage that the characteristics thereof are not influenced by the magnitude of the input signal and it performs or operates at high speed. However, in the prior art relay of this type, the relay is unstable near its tripping or actuation point. The comparison type distance relay is operated by composing simulation circuit and distinguishing the relative phase of the electric voltages involved. However, at a certain operating point the vector voltage to be phase compared becomes very small. Therefore the error in the phase comparison may be very large in the range where said vector becomes small. Because of this phenomenon the error may be increased especially when a fault occurs and the electric input current includes a highly modulated Wave.

For instance, referring to FIGURE 4, which illustrates Japanese Patent No. 448,761, the vector diagram will be described hereafter.

In FIGURE 4, IRg is a terminal voltage when electric current I runs through resistance at accident position, and IZi is another terminal voltage when the electric current I runs through a simulated impedance of the line from the point where the relay is located to the accident position.

If IZi and IRg are standard vectors, then both iZ-V and l "jRg are retarded more than IRg but advanced more than 121 when the electric voltage vector V is within the parallelogram shown by bold line or accident occurs in the established area. Therefore, by the detection of this condition, we are able to obtain a distance relay having quadrilateral characteristics. But it is diflicnlt to initiate exact comparison of phases, because the phase comparison signals I'Zi-V and VIRg at the points A and B have very small voltages, especially for short transmission lines.

In order to avoid such unstable operation in the prior art, two relays, for instance a mho relay and a reactance relay, are combined. Therefore, the circuit becomes complicated and highly sensitive amplifiers have to be employed.

One object of the present invention is to eliminate those defects stated above, providing a novel short distance, single element relay. Hereinafter, the present inice vention will be described referring to the accompanying drawings in which;

FIGURE 1, FIGURE 2 and FIGURE 3 show diagrams of characteristics for illustration of the present invention;

FIGURE 4 shows a diagram of characteristics for illustration of hitherto known relays;

FIGURE 5 shows a circuit diagram for obtaining predetermined vectors;

FIGURE 6 shows a wave form diagram for illustration;

FIGURE 7 shows a sequence showing an embodiment of a phase comparation apparatus; and

FIGURE 8 shows another block diagram showing another embodiment.

In FIGURE 1, which shows a vector diagram showing principle of operation of the short distance relay according to the present invention, I and V are electric current and voltage which are proportional to accidental electric current and voltage. Z Z Z and Z, are simulated impedance on the lines of a, b, c and d which are the elongated sides of a parallelogram forming a predetermined operation range and shown with bold lines. The voltages obtained from flowing electric current I through said impedances Z Z Z and 2, become vector voltages I2 I2 1Z and 1Z where:

Especially, 1Z is the vector voltage obtained by an electric current degrees out of phase.

Further, e e 2 and e, are signal vector voltages composed of said vector voltages IZ -IZ and V, where: 61=jZ V e =I Z V Z3=VIZ3 C4=VZ"Z4 Thus, if electric voltage V is within the parallelogram, the following matters are evident. (However, it is assumed that Z Z Z and Z, are not within the parallelogram.)

(1) e, and e;, are retarded more than IZ (IZ (2) e and 2 are advanced more than IZ (IZ (3) Although e or e is advanced more than a certain amount of phase determined by Z or Z against IZ (IZ respectively, neither one is retarded less than 12 02,

(4) Although 2 or e;, is retarded more than a certain amount of phase determined by Z or 2, against IZ (lZ neither one is advanced less than IZ (IZ Integrating above stated matters, we can say that (5) Each signal vector ee -e is retarded more than IZ (IZ and advanced more than IZ (IZ Then, if electric voltage exists outside of the parallelogram we can say as follows according to existence area of the voltage.

(1) If the electric voltage V is over line a, then e is advanced more than IZ (IZ (2) If the electric voltage V is on the left side of line b, then e is retarded more than IZ (lZ (3) If the electric voltage V is under the line 0, then e is advanced more than IZ (IZ (4) If the electric voltage V is on the right side of line a, then e is retarded more than IZ (IZ The condition stated above is effected only when the electric voltage V is within the parallelogram. Therefore, if this condition is detected, then we can obtain a distance relay having quadrilateral characteristics.

If IZ V and (2 :0, for instance, then it is difficult to distinguish the phase of signal 2, as has been stated, but according to the present invention, the condition (1) above stated or such condition that the signal e inevitably is advanced then 1Z is effected, so that there is no probability for the distance relay according to the present invention to cause erroneous motion because it is put into no work condition by the signal e independently on the signal e even though the signal e might be nearly zero.

Accordingly, for the operational limit value, we can obtain a very exact distance relay for distinguishing operation or not operation, without unstable motion as seen in the conventional relays. Also, as the secondary effect of the present invention, it is possible to simplify the circuit for operation of rectangular waves because even though either one of four signals of e -e for instance e may be of small value or nearly zero, three other vector voltages e e e may be selected large enough, by selection of 2 -2 (A circuit for operation of rectangular wave is for increasing accuracy of phase comparation by making rectangularly waved signal which corresponds to half wave of sine vector voltage.)

FIGURE 2 shows the case of an altered value of simulated impedance Z Z in FIGURE 1. The operative condition 5 in this case is that either of e e e and e is retarded more than 12 and advanced more than 12 Heretofore, there has been no offset. Hereafter, the offset case will be described. In this case, the simulated impedance Z may include a reactance component as Z =R +jX But even in this case, the standard vector has to be 12 which is shifted as much as impedance R and 12 which is shifted as much as XC. However, the impedance Z and Z in this case, are Z =Z +R Z =Z +XC, so that the part of the impedance element not offset can be utilized commonly. Here, the resistance R; determines the offset amount in the direction of the I axis, and the XC determines the offset amount in the direction of the i1 axis.

FIGURE 5 shows a circuit embodiment for obtaining each vector voltage stated above. FIGURE 5 shows the case of FIGURE 3 offset. (For obtaining a circuit of FIGURE 1 not offset, the space between both ends of R' and Q, has to be short-circuited.)

In the drawing, PT -PT denote voltage transformers, CT -CT denote current transformers and the transformation ratio is made 1:1, for simplification.

Considering the simulated impedance as including the windings of transformers CT -CT Obviously in FIGURE 5, e -e are sine waves. Modifying the positive or negative half waves into rectangular pulses of which the widths correspond to the half waves of the sine wave as shown in FIGURE 6a, then vector relations of 2 -2 can be drawn as shown in FIGURE 6b.

In FIGURE 6b, the sequence of pulse generation is shown, for convenience, as e' e' e' e' e' FIGURE 7 shows an example of a circuit which initiates phase comparison employing six vector voltage signals of e -e as 1Z 12 of FIGURE 5 are e,-, and 2 In FIGURE 7, e -e denote periods when each of the rectangular pulses shown in FIGURE 6 exists, a sequence of a contact point circuit to be a junction point a for making, and a junction point b for breaking. (X )(X (X denote auxiliary relays, of high speed for operation and returning. In such a circuit, if the e' makes as 2' shown in FIGURE 6 rises up, then e' e' are in a condition of break, and the relay (X is operated. If e' e' make before e' makes (b junction point of 2' breaks), then the relay (X is operated, and once the relay (X is operated, it is synchronized with the signal finally made (e'.; in FIGURE 6b).

If either of e' e' makes before e' then the relay (X is operated before the relay (X to lock the relay (X1), 50 that the relay (X is not operated. Unless either of e' -e' makes before junction point I; of 2' breaks, the relay is not operated also.

In other words, in FIGURE 7, there is the capability of distinguishing that either of e e is retarded more than e but advanced more than 2 FIGURE 6 shows only a case of junction pointed circuit, however, the present invention can be applied to a logic circuit as shown in FIGURE 8. In this case, if electric voltages 2 -2 are produced by a circuit of composed vectors as shown in FIGURE 5, and said electric voltages e e are applied to a switch circuit, such as a Schmitt trigger or the like, modified into rectangular waves as shown in FIGURE 6, and applied to the circuit shown in FIGURE 8, then a distance relay which generates an output only in the predetermined area of operation can be realized.

In FIGURE 6b and FIGURE 7, if at least one signal of e' e makes before e' or after e then no-operational condition may be established, so that it is obvious that there occurs no erroneous operation even though one of the remaining signals becomes zero or disturbed.

This invention is not confined to the embodiments shown and described, but may be changed or modified so long as such changes or modifications mark no material departure from the salient features of the invention as expressed in the appended claims.

What is claimed is:

1. A method of protecting an AC electric system from short circuit by a distance relay having quadrilateral characteristics comprising the steps of:

(a) forming voltages I2 I2 1Z I2 I2 and 12 by passing an electric current I proportional to the electric current of the electric system through six simulated impedance elements Z Z Z Z Z and Z6,

(b) making said simulated impedances to be upon extended sides of a parallelogram of a predetermined operating characteristic upon an impedance diagram,

(0) forming vector voltages e e e and e, by vectorially summing the voltage of the electric system to said voltages 1Z 1Z I2 and 12 (d) detecting location of short circuit by detecting whether all of said vector voltages are retarded more than said voltage 12 or advanced more than said voltage 12 2. A method according to claim 1 in which certain of said simulated impedance elements Z Z Z and 2.; also serve as simulated impedance elements Z and Z 3. A distance relay for protecting an AC electric system having a quadrilateral characteristic defined by a line impedance and a fault resistance on an impedance diagram comprising:

(a) means for providing a voltage e advanced by degrees more than the electric current of the system to be protected,

(b) means for providing a voltage e retarded by 180 degrees minus the line impedance phase angle of the system more than said voltage e by flowing the electric current of the system through a simulated impedance element having an impedance phase angle equal to the line impedance phase angle of the system,

(c) first vector sum means for providing voltages of 1Z I2 I2 and E, by flowing an electric current proportional to the electric current of the system through, respectively, a reference impedance Z cated upon an R axis in a first quadrant upon an impedance diagram, a reference impedance Z located upon a line showing the line impedance of the system in the impedance diagram, a reference impedance Z located upon a line parallel to the R axis in the second quadrant of the impedance diagram, and a reference impedance Z; located upon a line parallel to a line showing the line impedance and located within the fourth quadrant of the impedance diagram, none of said impedance elements appearing on the impedance diagram within a parallelogram defined by the line impedance and the fault resistance,

(d) second vector sum means which is connected to said first vector sum means and adapted to form vector sum AC voltages of e =IZ '-V, e =IZ -V, e VIZ e =V-IZ by vectorially summing the voltage of the system to each of said voltages 1Z 1Z Il and 1Z (e) a phase comparator for detecting that said voltages e e e and e; are retarded more than said voltage e but advanced more than said voltage e 4. The apparatus of claim 3 in which said phase comparator comprises:

(a) a signal converting circuit responsive to voltages e e e e e and e to form rectangular logic signal outputs e e e e e and e said rectangular logic signal outputs having a pulse width equal to a half wave of the sinusoidal wave of said AC voltages,

(b) first means for generating an output signal only when all of e e e and e are zero at the moment when e becomes one,

(0) second means for generating an output signal when all of e e e e and e becomes one while e remains at one due to the output of said first means,

(d) means for maintaining the output signal of said second means at least for a time equal to a half wave of the AC voltages whereby it is possible to detect that each of 2 e e and e,;, is retarded more than e but advanced more than e by detecting that 2 e e and e change from a zero state to a one state while said e becomes one after 2 has become one.

References Cited UNITED STATES PATENTS 3,325,688 6/1967 Riebs 317-36 3,340,434 9/ 1967 Riebs 317-36 3,369,156 2/1968 Souillard 31736 LEE T. HIX, Primary Examiner I. D. TRAMMELL, Assistant Examiner US. Cl. X.R 317-36 

